1. Field of the Invention
The present invention relates to a programmable impedance control circuit and more particularly to a programmable impedance control circuit that produces an internal impedance related to an external impedance.
2. Description of the Related Art
Recently, methods of combining on-chip parallel termination with series termination have been proposed for high speed data transmission (HSDT) applications. Parallel terminations exhibit superior signal integrity than series terminations, but consume more power. In on-chip terminated HSDT applications, full swing data is typically transmitted through a transmission line wherein an output driver acts as a source termination and a receiver acts as a parallel termination. In such a method, the swing level of the signal may be lowered. To implement on-chip termination, a matching resistor should be added to the output driver. However, because the output driver and the on-chip termination are disposed within a chip and characteristic impedance varies depending upon operating conditions, it is difficult to properly terminate with matching impedance with a fixed resistance.
Thus, it would be desirable to be able to program or adjust the impedance in such HSDT circuits, such as by a programmable impedance control circuit that can transmit information to an output driver and an on-chip termination by detecting an external resistance value. Such a programmable impedance control circuit matches impedance corresponding to an external resistance value when a user electrically connects the system to the external resistance, and also matches an internal impedance to an external impedance by actively updating a digital signal into a predetermined period in response to changes in voltage and temperature (hereinafter referred to as a VT change).
A conventional method of programmable impedance control allows a user to connect an external resistive device to a pin on a chip. The resistive device has a multiple predetermined resistance value, one of which is selected upon detection in the chip of voltage values, and a corresponding multiple times driver operated. The driver will usually be an array of MOS transistors, the impedance of the array varying with the number of transistors activated. For example, if an external resistance of xc3x975 is used (five times a predetermined resistance value), a MOS array driver will be activated to deliver the same impedance.
HSDT systems that require both series and parallel terminations, however, will require different impedances. For example, if an external resistance is xc3x975, a driver may require xc3x971 impedance, and a termination may require xc3x972 impedance. Another problem is that there may be mismatch errors in the measurement of the external impedance by the controller, because at high frequencies the external resistance may differ from the external impedance.
Disclosed is a programmable impedance control circuit, comprising an MOS array supplied with a first voltage; an external resistance having an external impedance, said external resistance equal to N times said external impedance; a pad outputting a second voltage obtained by combination of said MOS array and said external resistance; a reference voltage generator for generating a third voltage corresponding to N/(N+M) times said first voltage as a reference voltage for said second voltage; and wherein M times internal impedance is used for N times external impedance (N=M or Nxe2x89xa0M).
In another aspect of the invention, the reference generator outputs the third voltage from between a first resistance connected to the first voltage and a second resistance connected to ground and the ratio of the first resistance to the second resistance is equal to M to N.
In another aspect of the invention, the programmable impedance control circuit further comprises a detector; said detector adapted to detect an impedance corresponding to a reference voltage for the external resistance and output a feedback signal to the MOS array.
In another aspect of the invention, the detector generates a signal corresponding to an impedance of a reference voltage for an external resistance to output it and at the same time to feedback the signal to the MOS array.
In another aspect of the invention, the detector produces a current corresponding to an impedance of a reference voltage for an external resistance to output it and at the same time to feedback the current to the MOS array.
In another aspect of the invention, the MOS array is constructed with a plurality of PMOSs and turn on an additionally adjacent PMOS when the turned-on PMOS gate voltage reaches a drain voltage.
In another aspect of the invention, the MOS array includes a capacitance inserted between a gate and a source of the PMOSs.
In another aspect of the invention, the output of the pad and the detector are provided therebetween with a low-pass filter.
In another aspect of the invention, the programmable impedance control circuit comprises a pull-up circuit outputting a signal in response to a pull-up and a pull-down circuit outputting a signal in response to a pull down; wherein the circuit thereby feeds back the signal corresponding to the impedance generated by the detector of the pull-up circuit to produce a signal corresponding to an impedance of the detector of the pull-down circuit.
In another aspect of the invention, the programmable impedance control circuit comprises a pull-up circuit outputting a current in response to a pull-up and a pull-down circuit outputting a current in response to a pull down; wherein the circuit thereby feeds back the current corresponding to the impedance generated by the detector of the pull-up circuit to produce a current corresponding to an impedance of the detector of the pull-down circuit.
In another aspect of the invention, the programmable impedance control circuit includes a current mirror to reduce the up/down mismatch of the pull-up circuit and the pull-down circuit.
Disclosed is a programmable impedance control circuit using an M times internal impedance for an N times external impedance (Nxe2x89xa0M), comprising a pull-up circuit comprising a MOS array being supplied with a first voltage, an external resistance having an N times external impedance, a pad outputting a second voltage obtained in combination of the first MOS array and the external resistance, a first reference generator for generating a first reference voltage corresponding to N/(N+M) times of the first voltage as a first reference voltage for the second voltage outputted from the pad, a first comparator for comparing the second voltage with the first reference voltage to output an impedance in compliance the first reference voltage for the second voltage, and a first counter for generating a signal corresponding to the impedance outputted from the first comparator to output it to an up-driver and up-terminator and at the same time feeding back it to the first MOS array; and a pull-down circuit comprising a second MOS array being supplied with a first voltage and receiving a signal outputted from the first counter to control an impedance, a third MOS array connected to the second MOS array at one terminal and connected to ground at the other terminal, a second comparator for comparing the third voltage obtained by combination of the second MOS array and the third MOS array with the second reference voltage that is a half of the first voltage to output an impedance in compliance the second reference voltage for the third voltage, and a second counter for generating a signal corresponding to the impedance outputted from the second comparator to output it to a down-driver and down-terminator and at the same time feeding back it to the third MOS array.
In another aspect of the invention, the output of the pad and the first comparator are provided therebetween with a low-pass filter, and the first reference generator and the first comparator are provided therebetween with a low-pass filter.
In another aspect of the invention, the first reference generator outputs the first reference voltage from between a first resistance connected to the first voltage and a second resistance connected to ground, wherein the ratio of the first resistance and the second resistance is M to N.
Disclosed is a programmable impedance control circuit using an M times internal impedance for an N times external impedance (Nxe2x89xa0M), comprising a pull-up circuit comprising a PMOS current source being supplied with a first voltage or second voltage, an external resistance having an N times external impedance, a pad outputting a third voltage obtained in combination of the PMOS current source and the external resistance, a first reference generator for generating a fourth reference voltage corresponding to N/(N+M) times of the first voltage as a first reference voltage for the third voltage outputted from the pad, a first comparator for comparing the third voltage with the fourth voltage that is the first reference voltage to output an impedance in compliance the first reference voltage for the third voltage as an current to output it and at the same time feeding back it to the PMOS, a current mirror for copying the current from the first comparator, a second comparator for comparing the output voltage from the current mirror with the second reference voltage that is a half of the first voltage to output it, and a first counter for generating a signal corresponding to the impedance outputted from the second comparator to output it to an up-driver and up-terminator and at the same time feeding back it to the first MOS array; and a pull-down circuit comprising a second MOS array being supplied with a first voltage, an NMOS array connected to the second MOS array at one terminal and connected to ground at the other terminal, a third comparator for comparing the fifth voltage obtained by combination of the second MOS array and the NMOS array with the second reference voltage to output an impedance in compliance the second reference voltage for the fifth voltage, and a second counter for generating a signal corresponding to the impedance outputted from the third comparator to output it to a down-driver and down-terminator and at the same time feeding it back to the second MOS array.
In another aspect of the invention, the output of the pad and the first comparator are provided therebetween with a low-pass filter, and the first reference generator and the first comparator are provided therebetween with a low-pass filter.
In another aspect of the invention, the first reference generator outputs the fourth voltage from between a first resistance connected to the first voltage and a second resistance connected to ground, wherein the ratio of the first resistance and the second resistance is M to N.
In another aspect of the invention, the current source comprises a plurality of PMOSs and turns on an additionally adjacent PMOS when the gate voltage of the turned-on PMOS reaches a drain voltage, thereby extending the operational scope.
In another aspect of the invention, the current source is provided therein with a capacitor inserted between the gate and source of the each of the PMOSs.
Disclosed is a programmable impedance control circuit, comprising a voltage divider, said voltage divider comprising an MOS array supplied with a first voltage and an external resistance having an external impedance, said external resistance equal to N times said external impedance, said voltage divider outputting a second voltage, a reference voltage generator adapted to generate a third voltage corresponding to N/(N+M) times said first voltage as a reference voltage for said second voltage, and wherein M times internal impedance is used for N times external impedance (N=M or Nxe2x89xa0M).